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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. ad8316 dual output gsm pa controller features complete rf detector/controller function selectable dual outputs 49 db range at 0.9 ghz (?7.6 dbm to +1.5 dbm re 50 ) accurate scaling from 0.1 ghz to 2.5 ghz temperature-stable linear-in-db response log slope of 22 mv/db true integration function in control loop low power: 23 mw at 2.7 v power-down to 11 w applications single-band, dual-band, and triband mobile handsets (gsm, dcs, pcs, edge) wireless terminal devices transmitter power control functional block diagram out2 out1 flt1 vset flt2 10db comm offset compensation rfin det det det det det intercept positioning low noise gain bias low noise band gap reference output enable delay enbl vpos bsel hi-z 1.35 hi-z v? 10db 10db 10db 1.35 general description the ad8316 is a complete, low cost subsystem for the precise control of dual rf power amplifiers (pas) operating in the frequency range 0.1 ghz to 2.5 ghz and over a typical dynamic range of 50 db. the device is a dual-output version of the ad 8315 and intended for use in dual-band or triband cellular hand sets and other battery-operated wireless devices where a separate power control signal is required for each band. the logarithmic amplifier technique provides a much wider measurement range and better accuracy than is possible using controllers based on diode detectors. in particular, multiband and multimode cellu- lar designs can benefit from the temperature-stable (?0 c to +85 c) operation over all cellular telephony frequencies. its high sensitivity allows control at low input signal levels, thus reducing the amount of power that needs to be coupled to the detector. the selected output, out1 or out2, has the voltage range and current drive to directly connect to the gain control pin of most handset power amplifiers; the deselected output is pulled low to ensure that the inactive pa remains off. each output has a dedicated integrating filter capacitor that allows separate control loop settings for each pa. out1 and out2 can swing from 125 mv above ground to within 100 mv below the supply voltage. load currents of up to 12 ma can be supported. the setpoint control input applied to pin vset has an operating range of 0.25 v to 1.4 v. the input resistance of the setpoint interface is over 100 m ? , and the bias current is typically 0.5 a. the ad8316 is available in 10-lead msop and 16-lead lfcsp packages and consumes 8.5 ma from a 2.7 v to 5.5 v supply. when it is powered down, the sleep current is 4 a.
rev. c e2e ad8316especifications (v pos = 2.7 v, t a = 25 c, 52.3 on rfin, unless otherwise noted.) parameter conditions min typ max unit overall function frequency range 1 to meet all specifications 0.1 2.5 ghz input voltage range 1 db log conformance, 0.1 ghz e58.6 e10 dbv equivalent dbm range e45.6 +3 dbm logarithmic slope 2, 3 0.1 ghz 20.5 22.1 24.5 mv/db logarithmic intercept 2, 3 0.1 ghz e68 e74 e78 dbv equivalent dbm level e55 e61 e65 dbm rf input interface pin rfin input resistance 4 0.1 ghz 2.9 k input capacitance 4 0.1 ghz 1.0 pf outputs pins out1 and out2 minimum output voltage vset 200 mv, enbl high, rf input e60 dbm 0.1 0.15 0.25 v enbl low 0.025 v maximum output voltage r l > 800 2.45 2.6 v general limit 2.7 v v pos 5.5 v v pos e 0.1 v output current drive source 12 ma output buffer noise 25 nv/ hz hz hz hz hz h h h h h hz z
rev. c ad8316 e3e absolute maximum ratings * supply voltage vpos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v out1, out2, vset, enbl . . . . . . . . . . . . . . . . . . . 0 v, vpos rfin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 dbm equivalent voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 v internal power dissipation . . . . . . . . . . . . . . . . . . . . . . . 100 mw
rev. c e4e ad8316 input amplitude e dbm 0.6 e60 v set e v 0.4 0.2 e40 e30 e20 0 1.0 e10 0.8 10 1.6 1.2 1.4 e50 e73 e53 e43 e33 e13 e23 e3 e63 0.9ghz 1.9ghz 2.5ghz 0.1ghz input amplitude e dbv tpc 1. v set vs. input amplitude input amplitude e dbm 0.6 e60 v set e v 0.4 0 e40 e30 e20 0 1.0 e10 0.8 10 1.6 1.2 1.4 e50 e73 e53 e43 e33 e13 e23 e3 e63 0.2 e1 e2 e4 1 0 4 2 3 e3 input amplitude e dbv error e db e30 c +25 c +85 c e30 c +25 c +85 c tpc 2. v set and log conformance vs. input amplitude at 0.1 ghz input amplitude e dbm 0.6 e60 v set e v 0.4 0 e40 e30 e20 0 1.0 e10 0.8 10 1.6 1.2 1.4 e50 e73 e53 e43 e33 e13 e23 e3 e63 0.2 e1 e2 e4 1 0 4 2 3 e3 input amplitude e dbv error e db e30 c +25 c +85 c e30 c +25 c +85 c tpc 3. v set and log conformance vs. input amplitude at 0.9 ghz input amplitude e dbm e1 e60 e2 e4 e40 e30 e20 0 1 e10 0 10 4 2 3 e50 e73 e53 e43 e33 e13 e23 e3 e63 e3 input amplitude e dbv 1.9ghz 1.9ghz 0.9ghz 2.5ghz error e db 0.1ghz tpc 4. log conformance vs. input amplitude at selected frequencies input amplitude e dbm 0.6 e60 v set e v 0.4 0 e40 e30 e20 0 1.0 e10 0.8 10 1.6 1.2 1.4 e50 e73 e53 e43 e33 e13 e23 e3 e63 0.2 input amplitude e dbv error e db e1 e2 e4 1 0 4 2 3 e3 +25 c e30 c +85 c +25 c e30 c +85 c tpc 5. v set and log conformance vs. input amplitude at 1.9 ghz input amplitude e dbm 0.6 e60 v set e v 0.4 0 e40 e30 e20 0 1.0 e10 0.8 10 1.6 1.2 1.4 e50 e73 e53 e43 e33 e13 e23 e3 e63 0.2 input amplitude e dbv error e db e1 e2 e4 1 0 4 2 3 e3 +25 c e30 c +85 c +25 c e30 c +85 c tpc 6. v set and log conformance vs. input amplitude at 2.5 ghz etypical performance characteristics
rev. c ad8316 e5e input amplitude e dbm e1 e60 error e db e2 e4 e40 e30 e20 0 1 e10 0 10 4 2 3 e50 e73 e53 e43 e33 e13 e23 e3 e63 e3 input amplitude e dbv +85 c e30 c tpc 7. distribution of error at temperature after ambient normalization vs. input amplitude, 3 sigma to either side of mean, 0.1 ghz input amplitude e dbm e1 e60 error e db e2 e4 e40 e30 e20 0 1 e10 0 10 4 2 3 e50 e73 e53 e43 e33 e13 e23 e3 e63 e3 input amplitude e dbv +85 c e30 c tpc 8. distribution of error at temperature after ambient normalization vs. input amplitude, 3 sigma to either side of mean, 0.9 ghz frequency e ghz 700 0 resistance e 1000 100 0.5 1.5 2.0 1600 1300 2.5 3100 1900 2500 400 1.0 e1200 e1600 e2000 e600 e800 0 e400 e200 e1800 reactance e x 2800 2200 e1400 e1000 r (csp) freq msop chip-scale (lfcsp) (ghz) 0.1 0.9 1.9 2.5 r
rev. c e6e ad8316 frequency e ghz 0 slope e mv/db 0.5 1.0 23 21 20 1.5 2.0 2.5 +25 c 22 +85 c e30 c tpc 13. slope vs. frequency at selected temperatures v s e v 2.5 slope e mv/db 3.0 3.5 22.5 21.0 20.5 4.0 4.5 5.0 22.0 0.9ghz 0.1ghz 1.9ghz 2.5ghz 21.5 5.5 tpc 14. slope vs. supply voltage frequency e hz 1 amplitude e db 10 100 50 1k 10k 100k 1m 40 30 20 10 0 e10 e20 e30 e40 e50 e60 0 e20 e40 e60 e80 e100 e120 e140 e160 e180 e200 e210 phase e degrees 10m 100m c flt = 0pf c flt = 220pf tpc 15. ac response from vset to out1 and out2 frequency e ghz 0 intercept e dbm e66 e68 0.5 1.0 2.0 1.5 e64 e60 e62 e30 c +25 c +85 c 2.5 tpc 16. intercept vs. frequency at selected temperatures v s e v 2.5 intercept e dbm e68 e70 3.0 3.5 5.0 4.5 e64 e58 e60 0.1ghz 5.5 e62 e66 4.0 0.9ghz 1.9ghz 2.5ghz tpc 17. intercept vs. supply voltage noise spectral density e nv/
rev. c ad8316 e7e v s e v 2.7 v out e v 1.9 2.8 2.9 3.2 3.1 3.5 2.9 3.3 2.5 3.0 0ma 3.3 3.1 2.7 2.3 2.1 3.4 3.5 2ma 4ma 6ma 8ma 10ma 12 ma i load tpc 19. maximum out voltage vs. supply voltage by load current, ad8316 sourcing v enbl gnd v out gnd c flt = 68pf averaging = 16 samples 50mv per vertical division c flt = 220pf 1v per vertical division 2 s per horizontal division tpc 20. enbl response time, rise/fall time = 250 ns 52.3 2.7v ad8316 out2 flt2 vpos out1 comm flt1 bsel * rfin enbl vset c flt c flt h-p 8110a pulse generator tek p6204 fet probe r l 1k tek 1103 pwr supply tek tds3054 scope 0.1 f rf out h-p 8648b signal generator pulse out tek p6204 fet probe 2.7v * bsel high out1; bsel low out2 0.1ghz 60dbm tpc 21. test setup for enbl response time v s e v 2.7 v out e v 2.2 2.9 2.8 2.6 2.8 2.7 2.5 2.4 3.0 6ma 2.3 shading indicates 3 sigma 2ma tpc 22. distribution of maximum out voltage vs. supply voltage with 2 ma and 6 ma loads, 3 sigma to either side of mean, ad8316 sourcing gnd averaging = 16 samples 1v per vertical division 2 s per horizontal division gnd bsel input v out2 10mv per vertical division tpc 23. bsel response time, enbl grounded rf out h-p 8648b signal generator 0.1ghz e60dbm 52.3 2.7v ad8316 out2 flt2 vpos out1 comm flt1 bsel * rfin enbl vset c flt h-p 8110a pulse generator pulse out tek p6204 fet probe c flt tek p6204 fet probe r l 1k tek 1103 pwr supply tek tds3054 scope 0.1 f * bsel high out1; bsel low out2 tpc 24. test setup for bsel response time
rev. c e8e ad8316 gnd 2v per vertical division 2 s per horizontal division gnd 50mv per vertical division c flt = 220pf c flt = 68pf v out averaging = 16 samples v pos /v enbl 250ns rise time tpc 25. power-on and power-off response with vset grounded, rise/fall time = 250 ns gnd 2v per vertical division 2 s per horizontal division gnd 50mv per vertical division c flt = 68pf v out c flt = 220pf 1 s rise time averaging = 16 samples v pos /v enbl tpc 26. power-on and power-off response with vset grounded, rise/fall time = 1 s rf out h-p 8648b signal generator 0.1ghz e60dbm 52.3 ad8316 out2 flt2 vpos out1 comm flt1 bsel * rfin enbl vset c flt c flt h-p 8110a pulse generator r l 1k tek 1103 pwr supply tek tds3054 scope pulse out * bsel high out1; bsel low out2 ad811 tek p6204 fet probe 732 49.9 tek p6204 fet probe tpc 27. test setup for power-on and power-off response with vset grounded gnd pulsed rf input 0.1ghz, e3dbm 100ns per horizontal division gnd v out 1v per vertical division averaging = 16 samples tpc 28. pulse response time, full-scale amplitude change, open loop, c flt = 0 pf 1v per vertical division gnd pulsed rf input 0.1ghz, e3dbm 2 s per horizontal division gnd v out averaging = 16 samples tpc 29. pulse response time, full-scale amplitude change, open loop, c flt = 68 pf rfout h-p 8648b signal generator 0.1ghz 0dbm 52.3 3db pwr divider pulse mode in 10mhz ref out ad8316 c flt c flt h-p 8110a pulse generator pulse out trig out ext trig tek p6204 fet probe r l 1k tek 1103 pwr supply tek tds3054 scope 0.1 f 2.7v bsel high out1; bsel low out2 tek p6204 fet probe 2.7v 2.7v 0.4v * out2 flt2 vpos out1 comm flt1 bsel * rfin enbl vset tpc 30. test setup for pulse response time
rev. c ad8316 e9e 10mv per vertical division 2v per vertical division 2 s per horizontal division v out averaging = 16 samples v pos input 250ns rise time 1 s rise time tpc 31. power-on and power-off response with vset and enbl grounded rfout h-p 8648b signal generator 0.1ghz e60dbm 52.3 ad8316 out2 flt2 vpos out1 comm flt1 bsel * rfin enbl vset c flt c flt h-p 8110a pulse generator r l 1k tek 1103 pwr supply tek tds3054 scope pulse out * bsel high out1; bsel low out2 ad811 tek p6204 fet probe 732 49.9 tek p6204 fet probe tpc 32. test setup for power-on and power-off response with vset and enbl grounded general description and theory the ad8316 is a wideband logarithmic amplifier (log amp) with two selectable outputs suitable for dual-band/dual-mode power amplifier control. it is strictly optimized for power control appli- cations rather than for use as a measurement device. figure 1 shows its main features in block schematic form. the output pins, out1 and out2, are intended to be applied directly to the automatic power control (apc) pins of two distinct power amplifiers. when the band select pin, bsel, directs one of the controller outputs to servo its amplifier toward the setpoint indicated by the power control pin vset, the other output is forced to ground, disabling the second amplifier. each output has a dedicated filter pin, flt1 and flt2, that allows the filtering and loop dynamics for each control loop to be opti- mized independently. basic theory logarithmic amplifiers provide a type of compression in which a signal with a large range of amplitudes is converted to one of a smaller range. the use of the logarithmic function uniquely results in the output representing the decibel value of the input. the fundamental mathematical form is vv v v out slp in z = log (1) here v in is the input voltage and v z is called the intercept (volt- age) because when v in = v z the argument of the logarithm is unity, and thus the result is zero; v slp is called the slope (volt- age), which is the amount by which the output changes for a certain change in the ratio (v in /v z ). because log amps do not respond to power, but only to volt ages, and the calibration of the intercept is waveform dependent and only quoted for a sine wave signal, the equivalent power response can be written as vvpp out db in z = (e) (2) where the input power p in and the equivalent intercept p z are both expressed in dbm (thus, the quantity in the parentheses is simply a number of decibels), and v db is the slope expressed as so many mv/db. when base 10 logarithms are used, denoted by the function log 10 , v slp represents v/dec, and since a decade corresponds to 20 db, v slp /20 represents the change in v/db. for the ad8316, a nominal (low frequency) slope of 22 mv/db (corresponding to a v slp of 0.022 mv/db 20 db = 440 mv) was chosen, and the intercept v z was placed at the equivalent of e74 dbv, or 199 v rms, for a sine wave input. this corre- sponds to a power level of e61 dbm when the net resistive part of the input impedance of the log amp is 50 . however, both the slope and the intercept are dependent on frequency (see for example, tpc 13 and tpc 16). for a log amp with a slope v db of +22 mv/db and an inter- cept at e61 dbm, the output voltage for an input power of e30 dbm is 0.022 (e30 e [e61]) = 0.682 v. out2 out1 flt1 vset 325mv to 1.4v = 49db flt2 10db comm offset compensation rfin 10db 10db 10db det det det det det intercept positioning low noise gain bias low noise band gap reference output enable delay enbl vpos bsel 1.35 hi-z hi-z vei low noise rail-to-rail buffers 1.35 figure 1. block schematic of the ad8316
rev. c e10e ad8316 further details about the structure and function of log amps are provided in data sheets for other log amps produced by analog devices. the ad640 and ad8307 include detailed discussions of the basic principles of operation and explain why the inter cept depends on waveform, an important consideration when com plex modulation is imposed on an rf carrier. the intercept need not correspond to a physically realizable part of the signal range for the log amp. thus, for the ad8316, the specified intercept is e62 dbm at 0.9 ghz, whereas the lowest acceptable input for accurate measurement (+1 db error) is e48 dbm. at 2.5 ghz, the +1 db error point shifts to e52 dbm. this positioning of the intercept is deliberate and ensures that the vset voltage is within the capabilities of certain dacs, whose outputs cannot swing below 200 mv. figure 2 shows the 0.9 ghz response of the ad8316; the vertical axis represents the value required at the power control pin vset to null the control loop rather than the voltage at the out1 or out2 pins. p in 0.5v e67dbm v set 0 1.5v 1.0v 100 v 80dbv v in , dbv in 1mv 60dbv 10mv 40dbv 100mv 20dbv 1v (rms) 0dbv e47dbm e27dbm e7dbm +13dbm e62dbm slope = 22mv/db ideal 0.308v at e48dbm actual 1.408v at +2dbm figure 2. basic calibration of the ad8316 at 0.9 ghz controller-mode log amps the ad8316 combines the two key functions required for the measurement and control of the power level over a moder- ately w ide dynamic range. first, it provides the amplification needed to respond to small signals with a chain of four ampli- fier/ limiter cells, each with a small signal gain of 10 db and a bandwidth of approximately 4 ghz (see figure 1). at the output of each of these amplifier stages is a full-wave recti- fier, essentially a square-law detector cell that converts the rf signal voltages to a fluctuating current having an average value that increases w ith signal level. a passive detector stage is added ahead of the first stage. these five detectors are separated by 10 db, span ning 50 db of dynamic range. their outputs are in the form of a differential current, making summation a simple matter. it is readily shown that the summed output can closely approximate a logarithmic function. the overall accu- racy at the extremes of the total range, viewed as the deviation from an ideal logarithmic response, that is, the law-conformance error, can be judged by referring to tpc 4, which shows that errors across the central 40 db are moderate. other perfor- mance curves show how conformance to an ideal logarithmic function varies with supply voltage, temperature, and frequency. in a device intended for measurement applications, this current would be converted to an equivalent voltage to provide the log(v in ) function shown in equation 1. however, the design of the ad8316 differs from standard practice in that its output needs to be a low noise control voltage for an rf power ampli- fier, not a direct measure of the input level. further, it is highly desirable that this voltage be proportional to the time integral of the error between the actual input v in and a dc voltage v set (applied to pin 3, vset) that defines the setpoint, that is, a target value for the power level, typically generated by a dac. this is achieved by converting the difference between the sum of the detector outputs (still in current form) and an internally generated current proportional to vset to a single-sided cur rent-mode signal. this, in turn, is converted to a voltage (at flt1 or flt2, the low-pass filter capacitor nodes) to provide a close approximation to an exact integration of the error between the power present in the termination at the input of the ad8316 and the setpoint voltage. finally, the voltages developed across the ground referenced filter capacitors c flt are buffered by a special low noise amplifier of low voltage gain ( 1.35) and presented at out2 or out1 for use as the control voltage for the appropriate rf power amplifier. this buffer can provide rail-to-rail swings and can drive a substan- tial load current, in cluding large capacitors. note: the rf power delivered by the power amplifier is assumed to increase mono- tonically with an increasingly positive voltage on its apc control pin. band selection in the ad8316 relies on the fact that dual-band/ dual-mode amplifier systems require only one active amplifier at a time. this allows both amplifier outputs to share the rf input of the ad8316 (pin 1, rfin) as long as the inactive amplifier is disabled, i.e., it is not delivering rf power. in this case, power control is directed solely through the selected amplifier. the ad8316 ensures that the output control pin associated with the unselected amplifier pulls its apc pin to ground. it is assumed that the amplifier is essentially disabled when its apc pin is grounded. control loop dynamics to understand how the ad8316 behaves in a complete control loop, it is necessary to develop an expression for the current in the integration capacitor as a function of the input v in and the setpoint voltage v set . refer to figure 3. 1.35 c flt 4 flt1 9 vout1 v set v in i det setpoint interface 3 rfin 1 logarithmic rf detection subsystem i err vset i set = v set / 4.15k i det = i slp log 10 (v in /v z ) figure 3. behavioral model for the ad8316 with out1 selected first, write the summed detector currents as a function of the input: ii vv det slp in z = log ( / ) 10 (3) where i det is the partially filtered demodulated signal, whose exact average value will be extracted through the subsequent integration step; i slp is the current-mode slope, and has a value of 106 ma per decade (that is, 5.3 ma/db); v in is the input in
rev. c ad8316 e11e volts rms; and v z is the effective intercept voltage, which, as previously noted, is dependent on waveform but is 199 v rms for a sine wave input. now, the current generated by the setpoint interface is simply iv k set set = /. 415 (4) i err , the difference between this current and i det , is applied to the loop filter capacitor c flt . it follows that the voltage ap pearing on this capacitor, v flt , is the time integral of the difference current vs i i sc flt set det flt () ( ? )/ = (5) = vkivv sc set slp in z flt /. ? log ( / ) 415 10 (6) the control output v out is slightly greater than this, since the gain of the output buffer is 1.35. also, an offset voltage is delib- erately introduced in this stage, but this is inconsequential, since the integration function implicitly allows for an arbitrary constant to be added to the form of equation 6. the polarity is such that v out will rise to its maximum value for any value of v set greater than the equivalent value of v in . in practice, the output will rail to the positive supply under this condition unless the control loop through the power amplifier is present. in other words, the ad8316 seeks to drive the rf power to its maximum value w hen- ever it falls below the setpoint. the use of exact integration results in a final error that is theoretically zero, and the logarithmic detection law would ideally result in a constant response time following a step change of either the setpoint or the power level, if the power amplifier control function were likewise linear-in-db. this latter condition is rarely true, however, and it follows that the loop response time will, in practice, depend on the power level, and this effect can strongly influence the design of the control loop. equation 6 can be clarified by noting that it can be restated in the following way vs vv vv st out set slp in z () e log ( / ) = 10 (7) where v slp is the volts-per-decade slope from equation 1, having a value of 440 mv/dec, and t is an effective time constant for the integration, being equal to (4.15 k c flt )/1.35; the resis- tor value comes from the setpoint interface scaling equation 4 and the factor 1.35 arises as a result of the voltage gain of the buffer. so the integration time constant can be written as tc in s when c is ressed in nf flt flt = () 307 . exp (8) to simplify understanding of the control loop dynamics, begin by assuming that the power amplifier gain function actually is linear-in-db; for now, we will also use voltages to express the signals at the power amplifier input and output. let the rf output voltage be v pa and its input be v cw ; further, to characterize the gain control function, this form is used vgv pa o cw = 10 (/) vv out gsc (9) where g o is the gain of the power amplifier when v out = 0 and v gsc is the gain scaling. while few amplifiers will conform so conveniently to this law, it nevertheless provides a clearer starting point for understanding the more complex situation that arises when the gain control law is less than ideal. this idealized control loop is shown in figure 4. with some manipulation, it is found that the characteristic equation of this system is vs vv v v kgv v st out set gsc slp gsc o cw z o () ()/ log ( / ) = ? + 10 1 (10) where k is the voltage coupling factor from the output of the power amplifier to the input of the ad8316 (e.g., 0.1 for a 20 db coupler) and t o is a modified time constant (v gsc /v slp )t. this is quite easy to interpret. first, it shows that a system of this sort will exhibit a simple single-pole response, for any power level, with the customary exponential time domain form for either increasing or decreasing step polarities in the demand level v set or the carrier input v cw . second, it reveals that the final value of the control voltage v out will be determined by several fixed factors vt vv v v kgvv out set gsc slp gsc o cw z = () =? ()/ log(/) 10 (11) rf pa v cw rf drive: up to 2.5ghz v rf directional coupler c flt ad8316 response-shaping of overall control loop (external cap) v set v in = kv rf v out1 figure 4. idealized control loop for dynamic analysis, out1 selected example assume that the gain magnitude of the power amplifier runs from a minimum value of 0.316 (e10 db) at v out = 0 to 100 (40 db) at v out = 2.5 v. applying equation 9, we find g o = 0.316 and v gsc = 1 v. using a coupling factor of k = 0.0316 (that is, a 30 db directional coupler) and recalling that the nominal value of v slp is 440 mv and v z = 199 v for the ad 8316, we will first calculate the range of values needed for v set to control an output range of +32 dbm to e17 dbm. note that, in the steady state, the numerator of equation 7 must be zero, that is vv kv v set slp pa z = () log 10 (12) when v in is expanded to kv pa , the fractional voltage sample of the power amplifier output. now, for +32 dbm, v pa = 8.9 v rms, this evaluates to v max mv/ v v set () = () = 044 281 199 139 10 . log . (13) for a delivered power of e17 dbm, v pa = 31.6 mv rms, v min . mv/ v v set () = () = 044 1 0 199 0 310 10 . log . (14) note: the power range is 49 db, which corresponds to a voltage change of 49 db 22 mv/db = 1.08 v in v set .
rev. c e12e ad8316 the value of v out is of interest, although it is a dependent param- eter inside the loop. it depends on the characteristics of the power amplifier, and the value of the carrier amplitude v cw . using the control values derived above, that is, g o = 0.316 and v gsc = 1 v, and assuming that the applied power is fixed at e7 dbm (so that v cw = 100 mv rms), equation 11 shows v max v v v kg v v v v out set gsc slp o cw z () = () ? () = () ?
=?= log .. log .. ./ ... 10 10 139 1 044 0 0316 0 316 01 199 32 07 25 (15) v min v v v kg v v v out set gsc slp o cw z () = () ? () = () ?
=?= log .. log .. ./ .. 10 10 031 1 044 0 0316 0 316 01 199 07 07 0 (16) both results are consistent with the assumptions made about the amplifier control function. note that the second term is inde- pendent of the delivered power and is a fixed function of the drive power. finally, the loop time constant for these parameters, using an illustrative value of 2 nf for the filter capacitor c flt , evaluates to tv vt snf s o gsc slp = () = () () = / /. . . 1044 30 72 13 95 ? (17) practical loop at the present time, power amplifiers, or vgas preceding such amplifiers, do not provide an exponential gain characteristic. it follows that the loop dynamics (the effective time constant) will vary with the setpoint, since the exponential function is unique in providing constant dynamics. the procedure must therefore be as follows. beginning with the curve usually provided for the power output versus apc voltage, draw a tangent at the point on this curve where the slope is highest (see figure 5). using this line, calculate the effective minimum value of the vari able v gsc , and use it in equation 17 to determine the time constant. (note that the minimum in v gsc corresponds to the maximum rate of change in the output power versus v out .) for example, suppose it is found that, for a given drive power, the amplifier generates an output power of p 1 at v out = v 1 , and p 2 at v out = v 2 . then, it is readily shown that vvvpp gsc = ()() 20 21 21 e/e (18) this should be used to calculate the filter capacitance. the response time at high and low power levels (on the shoulders of the curve shown in figure 5) will be slower. note also that it is sometimes useful to add a zero in the closed-loop response by placing a resistor in series with c flt . a note about power equivalency users of the ad8316 must understand that log amps funda- mentally do not respond to power. for this reason, dbv (decibels above 1 v rms) are included in addition to the com- monly used metric dbm. the dbv scaling is fixed, independent of termination impedance, while the corresponding power level is not. for example, 224 mv rms is always e13 dbv, with one further condition of an assumed sinusoidal waveform; see the ad640 data sheet for more information about the effect of w ave- form on logarithmic intercept. this corresponds to a power of 0 dbm when the net impedance at the input is 50 . when this impedance is altered to 200 , however, the same voltage corresponds to a power level that is four times smaller (p = v 2 /r), or e6 dbm. a dbv level may be converted to dbm in the special case of a 50 system and a sinusoidal signal simply by adding 13 db. 0 dbv is then, and only then, equivalent to 13 dbm. e67dbm e47dbm e27dbm e7dbm +13dbm 33dbm 23dbm 13dbm 3dbm e7dbm p rf v out1 v 2, p 2 v 1, p 1 figure 5. typical power control curve therefore, the external termination added ahead of the ad8316 determines the effective power scaling. this often takes the form of a simple resistor (52.3 will provide a net 50 input), but more elaborate matching networks may be used. the choice of impedance determines the logarithmic intercept, that is, the input power for which the v set versus p in function would cross the baseline if that relationship were continuous for all values of v in . this is never the case for a practical log amp; the intercept (so many dbv) refers to the value obtained by the minimum- error straight-line fit to the actual graph of v set versus p in (more generally, v in ). where the modulation is complex, as in cdma, the calibration of the power response needs to be adjusted; the intercept will remain stable for any given arbitrary waveform. when a true power (waveform independent) response is needed, a mean-responding detector, such as the ad8361, should be considered. the logarithmic slope, v slp in equation 1, which is the amount by which the setpoint voltage needs to be changed for each decade of input change (voltage or power) is, in principle, independent of waveform or termination impedance. in practice, it usually falls off somewhat at higher frequencies, because of the de clining gain of the amplifier stages and other effects in the detector cells (see tpc 13). basic connections figure 6 shows the basic connections for operating the ad8316 and figure 7 shows a block diagram of a typical application. the ad8316 is typically used in the rf power control loop of dual mode and trimode mobile handsets where there is more than one rf power control line.
rev. c ad8316 e13e ad8316 out2 flt2 vpos out1 comm flt1 bsel rfin enbl vset 1 2 3 4 5 10 9 8 7 6 rfin +v s v set c flt1 v bsel v out1 v out2 c flt2 r1 52.3 c1 0.1 f +v s 2.7 to 5.5v figure 6. basic connections (shown with msop pinout) out1 directional coupler out2 flt2 vset flt1 rfin r1 52.3 c flt1 c flt2 attn dac gain control voltages rfin1 bsel band select rfin2 rx1 rx2 tx1 tx2 ant pwr amp figure 7. block diagram of typical application a supply voltage of 2.7 v to 5.5 v is required for the ad8316. the supply to the vpos pin should be decoupled with a low inductance 0.1 f surface-mount ceramic capacitor close to the device. the ad8316 has an internal input coupling capacitor, which negates the need for external ac coupling. this capacitor, along with the device?s low frequency input impedance of ap proxi- mately 3.0 k , sets the minimum usable input frequency to around 20 mhz. a broadband 50 input match is achieved in this example by connecting a 52.3 resistor between rfin and ground (comm). a plot of input impedance versus frequency is shown tpc 9. other matching methods are also possible (see the input coupling options section). in a power control loop, the ad8316 provides both the detector and controller functions. a number of options exist for coupling the rf signal from the power amplifiers (pa) to the ad8316 input. because only one pa output is active at any time, a single rf input on the ad8316 is sufficient in all cases. two directional couplers can be used directly at the pa outputs. the outputs of these couplers would be passively combined before being applied to the ad8316 rf input (in general, some additional attenuation will be required between the cou pler and the ad8316). another option involves using a dual-direc- tional coupler between the pa and t/r switch. this device has two inputs/outputs and a single-coupled output so that no exter- nal combiner is required. a third option is to use a single broadband directional coupler at the output of the transmit/receive (t/r) switch (the outputs from the two pas are combined in the t/r switch). this is shown in figure 7. this provides the advantage of enabling the power at the output of the t/r switch to be precisely set, elimi- nating any errors due to insertion loss and insertion loss variations of the t/r switch. a setpoint voltage is applied to vset from the controlling source, generally a dac. any imbalance between the rf input level and the level corresponding to the setpoint voltage will be corrected by the selected output, out1 or out2, which drives the gain control terminal of the pas. this restores a balance between the actual power level sensed at the input of the ad 8316 and the demanded value determined by the setpoint. this assumes that the gain control sense of the variable gain element is posi- tive; that is, an increasing voltage from out1 or out2 will tend to increase gain. the outputs can swing from 100 mv above ground to within 100 mv of the supply rail and can source up to 12 ma. (a plot of maximum output voltage versus output current is shown in tpc 19.) out1/out2 are capable of sinking more than 200 a. range on vset and rf input the relationship between rf input level and the setpoint volt- age follows from the nominal transfer function of the device (see tpcs 2, 3, 5, and 6). at 0.9 ghz, for example, a voltage of 1 v on vset indicates a demand for e17 dbm (e30 dbv) at rfin. the corresponding power level at the output of the power am pli- fier will be greater than this amount due to the attenuation through the directional coupler. for setpoint voltages of less than approximately 200 mv and rf input amplitudes greater than approximately e50 dbm, v out will remain unconditionally at its minimum level of approximately 250 mv. this feature can be used to prevent any spurious emissions during power-up and power-down phases. above 250 mv, vset will have a linear control range up to 1.4 v, corresponding to a dynamic range of 49 db. this results in a slope of 22.2 mv/db or approximately 45.5 db/v. transient response the time domain response of power amplifier control loops, using any kind of controller, is only partially determined by the choice of filter which, in the case of the ad8316, has a true integrator form 1/st, as shown in equation 7, with a time con- stant given by equation 8. the large signal step response is also strongly dependent on the form of the gain control law. never- theless, some simple rules can be applied. when the filter capacitor c flt is very large, it will dominate the time domain response, but the incremental bandwidth of this loop will still vary as v out traverses the nonlinear gain control function of the pa, as shown in figure 5. this bandwidth will be highest at the point where the slope of the tangent drawn on this curve is greatest?that is, for power outputs near the center of the pa?s range?and will be much reduced at both the minimum and the maximum power levels, where the slope of the gain control curve is lowest, due to its s-shaped form. using smaller values of c flt , the loop bandwidth will generally increase, in inverse proportion to its value. eventually, however, a secondary effect will appear, due to the inherent phase lag in the power am plifier?s control path, some of which may be due to parasitic or deliber- ately added capacitance at the out1 and out2 pins. this results in the characteristic poles in the ac loop equation moving off the real axis and thus becoming complex (and somewhat resonant). this is a classic aspect of control loop design. the lowest permissible value of c flt needs to be determined experimentally for a particular amplifier and circuit board lay- out. for gsm and dcs power amplifiers, c flt will typically range from 150 pf to 300 pf. in many cases, some improvement in the worst-case response time can be achieved by including a small resistance in series with c flt ; this generates an additional zero in the closed-loop trans- fer function, which will serve to cancel some of the higher-order
rev. c e14e ad8316 poles in the overall loop. a combination of main capacitor c flt shunted by a second capacitor and resistor in series will also be useful in minimizing the settling time of the loop. mobile handset power control example figure 8 shows a complete power amplifier control circuit for a dual-mode handset. the rf3108 (rf micro devices), dual- input, trimode (gsm, dcs, pcs) pa is driven by a nominal power level of 6 dbm at both inputs and has two gain control lines. some of the output power from the pa is coupled off using a dual-band directional coupler (murata part number ldc15d190a0007a). this has a coupling factor of approxi- mately 20 db for the gsm band and 15 db for dcs and an insertion loss of 0.38 db and 0.45 db, respectively. because the rf3108 transmits a maximum power level of approximately 35 dbm for gsm and 32 dbm for dcs/pcs, additional at tenua- tion of 20 db is required before the coupled signal is applied to the ad8316. this results in peak input levels of e5 dbm (gsm) and e3 dbm (dcs). while the ad8316 gives a linear response for input levels up to +3 dbm, for highly temperature-stable performance at maximum pa output power, the maximum input level should be limited to approximately e3 dbm (see tpc 3 and tpc 5). this does, however, reduce the sensitivity of the circuit at the low end. the operational setpoint voltage, in the range 250 mv to 1.4 v, is applied to the vset pin of the ad8316. this will typically be supplied by a dac. the desired output is selected by applying a high or low signal to the bsel pin (hi = out1, lo = out2). the selected output directly drives the level control pin of the power amplifier. in this case a minimum supply voltage of 2.9 v is required and v out reaches a maximum value of approxim ately 2.6 v while delivering about 5 ma to the pa?s v apc input. for power amplifiers with lower v apc input ranges, a corresponding low power supply to the ad8316 can be used. for example, on a 2.7 v supply, the voltage on out1/out2 can come to within approximately 100 mv of the supply rail. this will depend, how- ever, on the current draw (see tpc 19). during initialization and completion of the transmit sequence, v out should be held at its minimum level of 250 mv by keeping v set below 200 mv. in this example, v set is supplied by an 8-bit dac that has an output range from 0 v to 2.55 v or 10 mv per bit. this sets the control resolution of v set to 0.4 db/bit (0.04 db/mv
rev. c ad8316 e15e enable and power-on the ad8316 may be disabled by pulling the enbl pin to ground. this reduces the supply current from its nominal level of 8.5 ma to 3 a at 2.7 v. the logic threshold for turning on the device is at 1.8 v at 2.7 v. a plot of the enable glitch is shown in tpc 20. alternatively, the device can be completely disabled by pulling the supply voltage to ground; enbl would be connected to vpos. the glitch in this mode of operation is shown on tpc 25 and tpc 26. if vpos is applied before the device is enabled, a narrow glitch of less than 50 mv will re sult. this is shown in tpc 31. in both situations, the voltage on v set should be kept below 250 mv during power-on and power-off, preventing any unwanted transients on v out . input coupling options the internal 5 pf coupling capacitor of the ad8316, along with the low frequency input impedance of 3 k , result in a high- pass input corner frequency of approximately 20 mhz. this sets the minimum operating frequency. figure 9 shows three options for input coupling. a broadband resistive match can be implem ented by connecting a shunt resistor to ground at rfin. this 52.3 resistor (other values can also be used to select different overall input impedances) combines with the input impedance of the ad8316 (3 k
rev. c e16e ad8316 ad8316 out2 flt2 vpos out1 comm flt1 bsel rfin enbl vset 1 2 3 4 5 10 9 8 7 6 vpos ad8031 r5 10k r6 17.8k c3 0.1 f r8 10k r7 16.2k c5 0.1 f r2 52.3 r1 0 vpos b sw1 j3 vset lk1 c4 (open) r10 (open) out1(a) out2(b) vpos c1 0.1 f r3 0 j2 out1 c2 (open) r4 (open) r12 0 r9 (open) c7 (open) j4 out2 out1 (a) out2 (b) lk2 vpos c6 (open) r11 (open) sw2 sw3 a j1 input figure 10. schematic of evaluation board (msop) j1 j3 vpos sw1 a b input vset lk1 r1 0 c4 (open) r10 (open) out1 (a) out2 (b) vpos sw2 c5 0.1 f vpos r2 52.3 c6 (open) r11 (open) c1 0.1 f vpos r12 0 c2 (open) r4 (open) r3 0 r9 (open) c7 (open) r7 16.2k c3 0.1 f out1 (a) out2 (b) sw3 lk2 r8 10k r6 17.8k r5 10k ad8031 j2 out1 j4 out2 ad8316 rfin enbl vset flt1 bsel flt2 comm out1 vpos out2 comm nc nc nc nc nc nc = no connect 1 2 3 4 12 11 10 9 5678 13 14 15 16 figure 11. schematic of evaluation board (lfcsp) r in c in c c ad8316 r shunt 52.3 rfin a. broadband resistive r in x2 c in c c ad8316 rfin x1 b. narrow-band reactive r in c in c c ad8316 rfin r attn stripline antenna pa c. series attenuation figure 9. input coupling options
rev. c ad8316 e17e table ii. evaluation board configuration options component function default condition tp1, tp2 supply and ground vector pins. not applicable sw1 device enable. when in position a, the enbl pin is connected to vpos and sw1 = a the ad8316 is in operating mode. in position b, the enbl pin is grounded, putting the device into power-down mode. sw2 band select. when in position a (out1), the bsel pin is connected to vpos sw2 = out1 and the ad8316 out1 is in operation mode. in position b (out2), the bsel pin is grounded and the ad8316 out2 is in operation while out1 pin is shut down. r1, r2 input interface. the 52.3 resistor in position r2 combines with the ad8316?s r2 = 52.3 (size 0603) internal input impedance to provide a broadband input impedance of around r1 = 0 (size 0402) 50 . a reactive match can be implemented by replacing r2 with an inductor and r1 (0 ) with a capacitor. in addition, the rf microstrip line has been provided with a clean mask ground plane to provide additional matching. note that the ad8316?s rf input is internally ac-coupled. r3, r4, r12, output interface. r4 and c2, r9 and c7 can be used to check the response r4 = c2 = open (size 0603) r9, c2, c7 capacitive and resistive loading, respectively. r3/r4 and r12/r9 can be used to r9 = c7 = open (size 0603) reduce the slope of out1 and out2. r3 = r12 = 0 (size 0603) c1, c5 power supply decoupling. the nominal supply decoupling consists of c1 = c5 = 0.1 f (size 0603) a 0.1 f capacitor. c4, c6, r10, filter capacitors/resistors. the response time of out1, out2 can be modified c4 = c6 = open (size 0603) r11 by placing the capacitors between flt1, flt2 and resistors r10, r11 r10 = r11 = open (size 0603) to ground. lk1, lk2 measurement mode. a quasi-measurement mode can be implemented by lk1, lk2 = installed installing lk1 and lk2 (connecting an inverted out1 or out2 to vset) to yield the nominal relationship between rfin and vset. in this mode, a large capacitor (0.01 f or greater) must be installed in c4 and c6 and a 0 resistors to ground in r10 and r11. to select out1 or out2, sw3 must be in the out1 position or the out2 position, respectively. sw3 measurement mode output select. when in measurement mode, output 1 sw3 = out1 or output 2 can be selected by positioning sw3 to the out1 position or the out2 position, respectively.
rev. c e18e ad8316 figure 12. silkscreen of component side (msop) figure 13. layout of component side (msop)
rev. c ad8316 e19e outline dimensions 16-lead lead frame chip scale package [lfcsp] 3 mm 3 mm body (cp-16-3) dimensions shown in millimeters 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq 1.65 1.50 1.35 bottom view sq * 16 5 13 8 9 12 4 * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba
rev. c c02192e0e1/04(c) e20e ad8316 revision history location page 1/04edata sheet changed from rev. b to rev. c. changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 12/03edata sheet changed from rev. a to rev. b. updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edit to figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3/03edata sheet changed from rev. 0 to rev. a. addition of lfcsp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to tpc 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 tpc 9 replaced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edit to tpc 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 edits to example section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 edits to input coupling options section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 addition of new figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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